Staff Digital Verification Engineer

Description Position Summary We are looking for a highly motivated Staff Digital Verification Engineer with 6-10 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM , along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is required, while experience with fault injection simulatio…