Functional Verification Engineer

Project Role : Functional Verification Engineer Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out. Must have skills : SoC Verification Good to have skills : NA Minimum …